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Si9978
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SO-24
(Wide Body)
V DD
EN/EN A
DIR/IN A
1
2
3
24
23
22
V+
CAP A
S A
PWM/EN B
QS/IN B
4
5
21
20
GT A
GB A
ORDERING INFORMATION
MODE
BRK
CL/FAULT B
FAULT/FAULT A
6
7
8
9
19
18
17
16
CAP B
S B
GT B
GB B
Part Number
Si9978DW
Si9978DW-T1
Lead (Pb)-Free
Part Number
Si9978DW-T1—E3
Temperature
Range
? 40 to 85 _ C
Package
SOIC-24
(Wide Body)
NC
R A /C A
R B /C B
10
11
12
15
14
13
GND
IL B +
IL A +
Top View
PIN DESCRIPTION
Pin 1: V DD
V DD is an internally generated voltage. It is connected to this
pin to allow connection of a decoupling capacitor. A minimum
of 1 m F is recommended.
Pin 2: EN/EN A
The EN input allows normal operation when at logic “1”, and
turns all gate drive outputs off when at logic “0”. When the
mode pin is at logic “1”, EN controls the entire H-bridge. When
the mode pin is at logic “0”, this pin becomes the ENABLE pin
for half-bridge A.
Pin 3: DIR/IN A
The function of this pin is determined by the MODE pin. When
the MODE pin is at logic “1”, it is the DIR pin, and when MODE
is at logic “0”, it is the IN A pin.
As the DIR input, it is the direction control for the H-bridge, and
determines which diagonal pair of power MOSFETs is active.
A logic “1” turns on GT A and enables GB B , while a logic “0”
turns on GT B and enables GB A . When implementing an
anti-phase PWM control, the DIR input serves as the PWM
input.
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4
As the IN A pin, it is the input that controls the “A” half-bridge.
When at logic “1”, the high-side MOSFET is turned on, and
when at logic “0”, the low-side MOSFET is turned on.
Pin 4: PWM/EN B
With the mode pin at logic “1”, this pin is the PWM input. It
controls the switching of the active diagonal pair. A logic “1”
turns the active MOSFETs on, while a logic “0” turns it off. The
QS input determines whether the bottom or both bottom and
top MOSFETs are switched. When implementing an
anti-phase PWM control, the PWM input is connected to a logic
“1”. When the mode pin is at logic “0”, this pin becomes the
ENABLE pin for half-bridge B.
Pin 5: QS/IN B
With the mode pin at logic “1”, this input determines whether
the bottom MOSFETs of the H-bridge or both bottom and top
MOSFETs switch in response to the PWM signal. A logic “1” on
this input enables only the bottom MOSFETs. This is the
default condition as this pin is pulled up internally. When this
pin is pulled to ground, both the bottom and top MOSFETs are
enabled.
This input controls the B half-bridge when the MODE pin is at
logic “0”. When at logic “1”, the high-side MOSFET is turned on,
and when at logic “0”, the low-side MOSFET is turned on.
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
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